CMOS circuitry and ECL circuitry are typically considered to be incompatible due to the significantly different voltage swings and levels employed by each. While it is possible to overcome such differences by providing attenuators or amplifiers, the use of such additional components results in undesirable signal delays, increased power consumption, and a requirement for additional circuit area.
A desirable goal is to provide an arrangement by which CMOS and ECL circuits may communicate directly with one another without requiring special interfaces. However, conventional practice has not achieved this goal.
The following chronologically ordered U.S. Patents are illustrative of various conventional CMOS/ECL interfacing techniques and related technology.
In U.S. Pat. No. 4,656,375, issued Apr. 7, 1987, entitled "Temperature Compensated CMOS to ECL Translator", Lauffer et al. disclose circuitry that provides a complimentary switching circuit for switching an output terminal between two voltage levels corresponding to the logic levels of an ECL logic circuit. A normally unused ECL logic circuit provides the two voltage levels to a complimentary switch for achieving a temperature compensation function.
In U.S. Pat. No. 4,782,251, issued Nov. 1, 1988, entitled "Level Conversion Circuit", Tsugaru et al. describe a level conversion circuit for converting CMOS level signals to ECL level signals. A differential amplifier circuit is inserted between a high potential voltage source and a low potential voltage source and selects a current path flowing therebetween. A bipolar transistor is coupled to a collector potentials of one of the bipolar transistors and outputs ECL logic levels from its emitter terminal.
In U.S. Pat. No. 4,794,317, issued Dec. 27, 1988, entitled "ECL-To-CMOS Level Conversion For Use in ECL-BICMOS Circuit", van Tran discloses an ECL-to-CMOS level shifter. The level shifter uses a CMOS convertor that is coupled directly to an ECL buffer. A voltage drop across a resistor shifts the ECL logic levels down to a trip point of the CMOS convertor. The voltage drop across this resistor is set such that the trip point of the CMOS convertor is at half the output voltage of the ECL buffer.
U.S. Pat. No. 4,806,799, issued Feb. 21, 1989, entitled "ECL to CMOS Translator", to Pelley, III et al., discloses an ECL-to-CMOS translator. The translator includes an NPN transistor having a base that receives an ECL output signal. A control circuit couples the emitter of the NPN transistor to an intermediate node in response to the ECL output signal switching.
U.S. Pat. No. 4,864,159, issued Sep. 5, 1989, entitled "ECL to CMOS Transition Amplifier", to Cornellissen, discloses an amplifier for adjusting logic levels used in ECL logic to logic levels used in CMOS logic. The approach of Cornellissen is to employ first and second parallel arranged branches coupled between first and second supply voltage lines.
In U.S. Pat. No. 4,890,019, issued Dec. 26, 1989, entitled "Bilingual CMOS to ECL Output Buffer", Hoyte et al. describe an output buffer that converts a standard CMOS signal from a (0, +5) volt domain into a standard ECL signal in a (-0.8, -1.6) volt domain. A pair of "grounded-well" CMOS transistors are employed by the output buffer.
In commonly assigned U.S. Pat. No. 4,897,564, issued Jan. 30, 1990, entitled "BICMOS Driver Circuit for High Density CMOS Logic Circuits" Chen discloses a BICMOS driver circuit with voltage swing levels shifted with respect to a following CMOS logic circuit voltage level. This permits the BICMOS driver circuit to generate a low logic level that is substantially below the threshold voltage of the CMOS logic, and a high logic level that overdrives the CMOS logic.
U.S. Pat. No. 4,906,871, issued Mar. 6, 1990, entitled "Level Shift Circuit for Converting a Signal in an ECL Level into a Signal in a CMOS Logic Level", to Iida, discloses an AC coupled level shift circuit that includes a capacitor that is coupled at a first electrode to an output stage of an ECL circuit, a MOS inverter that is connected to a second electrode of the capacitor, and an output node of the MOS inverter is coupled to an input stage of a CMOS circuit. A bias circuit is provided for applying a bias voltage to the input node of the MOS inverter.
In U.S. Pat. No. 4,912,347, issued Mar. 27, 1990, entitled "CMOS to ECL Output Buffer" Morris discloses a CMOS to ECL output buffer that includes a current source that provides a current for establishing an ECL logic "zero" output voltage. The current from the current source also tracks variations in the resistance of a resistor to maintain essentially constant a voltage difference between an ECL logic "one" and the ECL logic "zero" output voltage.
Finally, in U.S. Pat. No. 4,914,321, issued Apr. 3, 1990, entitled "BIMOS Level Convertor", by D. E. Davis, there is described a BIMOS level convertor that includes a differential circuit having a common biasing network. A MOS transistor in one portion of the differential circuit receives a MOS level input signal and provides an ECL level output signal. The differential circuit also includes a bipolar transistor that is biased by the MOS transistor to generate a complimentary ECL level output signal. This combination is said to provide a single ended MOS to differential ECL interface.
What is not taught by these U.S. Patents, and what is thus one object of the invention to provide, is an arrangement whereby CMOS and ECL circuits may directly drive one another.
It is a further object of the invention to provide an ECL circuit that may be directly coupled to a CMOS circuit without requiring intermediate interface circuitry.